In the production of microelectronic devices, integrated circuits utilize multilevel wiring structures for interconnecting regions within devices and for interconnecting one or more devices within integrated circuits. Conventionally, forming interconnect structures begins with forming a lower level of wiring followed by the deposition of an interlevel dielectric layer and then a second level of wiring, where the first and second wiring levels may be connected by one or more metal filled vias.
Conventional interconnect structures employ one or more metal layers. Each metal layer is typically made from aluminum alloys or tungsten. Interlevel and intralevel dielectrics (ILDs), such as silicon dioxide (SiO2), are used to electrically isolate active elements and different interconnect signal paths from each other. The electrical connections between different interconnect levels are made through vias that are formed in the ILD layers. Typically, the vias are filled with a metal, such as tungsten.
Recently, there has been great interest to replace SiO2 with low-dielectric constant (“low-k”) materials as the intralevel and/or interlevel dielectrics in interconnect structures. Examples of low-k dielectrics include polymer-based low-k dielectric materials, which may or may not comprise a polymer, or carbon-doped oxide having a low dielectric constant. An example of a low-k b-staged polymer is SiLK™ (trademark of The Dow Chemical Company) having a composition including 95% carbon. An example of a low-dielectric carbon doped oxide is SiCOH. It is desirable to employ low-k materials as insulators in IC interconnect because these low-k materials reduce the interconnect capacitance. Accordingly, these low-k materials increase the signal propagation speed while reducing cross-talk noise and power dissipation in the interconnect.
The main problem with low-k materials is that they lack mechanical rigidity and easily crack when subjected to thermal and mechanical stresses. Conventionally, in via processing the interlevel dielectric layer is etched to provide an opening in which a metal interconnect is later formed to provide a means of communication between metal layers. Despite the ability of low-k materials to reduce the interconnect capacitance, forming via interconnects through low-k interlayer dielectrics having low mechanical strength produces a number of disadvantageous results. For example, if the dielectric is bent or is mechanically stressed, the interconnect metal may break within the via. Additionally, differences between the thermal coefficient of expansion of the metal interconnect and low-k interlevel and/or intralevel dielectrics produce further stresses that contribute to via breakage and chip failure.
Attempts to overcome the above disadvantages have resulted in further difficulties. For example, referring to FIG. 1, attempts have been made to use a thick refractory metal liner 22 to reinforce the low-k dielectric interlevel dielectric 35 and interconnect via 24. Via interconnects 24 are typically formed from a low resistance interconnect metal, such as copper. The high resistivity refractory metal liner 22 has a resistance much greater than the low resistance copper used in the via interconnect 24 and wiring 25, 26. Therefore, introducing refractory metal within the via opening 24 disadvantageously increases the resistance of the interconnect structure 10.
Additionally, refractory metals, such as Ta, are difficult to deposit using chemical vapor deposition. Therefore, the refractory metal liner 22 is typically deposited using sputter deposition. Sputter deposition fails to sufficiently deposit metal along the via 24 sidewalls of the low-k ILD dielectric 35. In order to deposit the required thickness of metal along the sidewalls of the via 24, a very thick layer of refractory metal 22 must be sputter deposited atop of the lateral surfaces. By increasing the thickness of the refractory metal liner 22, greater amounts of high resistance refractory metal is introduced into the via opening. Additionally, introducing high resistance refractory metal within the via opening 24 reduces the diameter of the low resistance component of the via interconnect 24 further increasing it's resistance.
In view of the above, a low resistivity via interconnect is needed having thin mechanically rigid dielectric layers.